Stage - Development of an FPGA based AXI4 lite to BiSS IP

Internship project at John Cockerill Defense: 

The goal of this thesis is to develop a proof-of-concept of an IP which implements a BiSS through a AXI4 lite register interface. An existing SSI IP will be adapted to be able to deal with both SSI and BiSS protocols. The IP must be integrated into a Xilinx FPGA technology (e.g. zynq ultrascale+). The proof-of-concept shall be developed on a Xilinx development board.The student will start by understanding the SSI and BISS protocols, then the architecture and the integration of IPs in a Xilinx FPGA.The student will analyze the existing AXI4 Lite SSI IP. The student will define and evaluate the development boards and FPGA needs.

The student will create an AXI4 lite with a BiSS interface IP. The student will then validate the behavior of the IP using simulation testing tools (VHDL and/or UVM testbench) .The student will test the IP integrated in a small software project in real conditions on hardware. The student must develop the software and access the stability and the performances of the design.The student will then merge the logic of the BiSS IP into the SSI one. The student will have to adapt the register map of the SSI IP to integrate the developed IP. The student will also adapt its simulation tests and test the final IP on hardware.

The student need to be avaible for at least 3 months. 

Profile : 

• Student in electronic/electro-mechanical engineering with an master's degree education level
• The student need to understand english and french