Stage - Development of an FPGA based AXI4 lite interface

Internship project at John Cockerill Defense: 

The goal of this thesis is to develop a proof-of-concept of an IP which interfaces multiple UARTs through a single AXI4 lite register interface. The IP must be integrated into a Xilinx FPGA technology (e.g. zynq ultrascale+). The IP should interface up to 8 UART interface at the same time.The UART must have configurable baudrate. The register map interface should be designed in a efficient way so that data can be pushed or retrieved fastly .The proof-of-concept shall be developed on a Xilinx development board.

The student will start by understanding the UART protocol, then the architecture and the integration of IPs in a Xilinx FPGA. The student will do some research on existing IP. The student will define and evaluate the development boards and FPGA needs.The student will create an AXI4 lite with a single UART IP. The IP can be coded from scratch or based on existing IPs. The student will then validate the behavior of the IP using simulation testing tools (VHDL and/or UVM testbench) .The student will modify the IP and add several UART interface (up to 8). The student will then check the behavior of the IP on simulation.The student will test the IP integrated in a small software project in real conditions on hardware. The student must develop the software and access the stability and the performances of the design.

The student need to be avaible for at least 3 months. 

Profile : 

• Student in electronic/electro-mechanical engineering with an master's degree education level
• The student need to understand english and french